1. Field of the Invention
The present invention generally relates to techniques for designing and manufacturing integrated circuits (ICs). More specifically, the present invention relates to techniques and systems for performing lithography verification for a double-patterning process.
2. Related Art
Advances in IC manufacturing technology have enabled minimum feature sizes on IC chips to decrease. In fact, the current minimum feature size is significantly smaller than the wavelengths of light used in conventional optical imaging systems. The need for 32-nm node technology has arrived before accompanying high refractive index materials or extreme-ultraviolet (EUV) light source has become available for producing such small nodes. While 193-nm water immersion lithography has been considered a promising technology to push beyond the 32-nm node, this lithography technique generally requires patterning features at an effective dielectric constant (k1) below the theoretical limit of 0.25. However, crossing this physical limit may not be possible unless the minimum pitch requirement is relaxed through splitting the design mask layout into two masks, and printing the mask using a sequence of two separate exposures—which is often referred to as a double-patterning technique (DPT).
Although DPT makes 32-nm and even smaller half-pitch designs feasible, this technique poses new challenges to the lithography verification process, which is often referred to as “lithography rule checking” (LRC). Typically, two approaches are used to perform a conventional single-patterning LRC, which are illustrated in FIG. 2. The first approach is referred to as a “contour-based” LRC, which is illustrated in the top plot of FIG. 2. This approach first simulates contours for the full design layout (e.g., contour 202 of polygon 204), and then performs pinching, bridging, and other types of lithography checking on the simulated contours (e.g., a pinching checking 206 along the narrowest direction on contour 202).
The second LRC approach is referred to as a “check-figure” based LRC. Typically, a check-figure based LRC “pre-filters” a layout to identify both “safe” areas within a layout and “risky” areas within the layout. Subsequently, the safe areas are assigned with sparse intensity evaluation points because these areas are less likely to have problem, and the risky areas with dense intensity evaluation points because these are areas where errors are likely to occur. For example, FIG. 2 illustrates two types of check-figure based pinching LRC verification. Specifically, the middle plot in FIG. 2 illustrates a “gauge-based” LRC, which evaluates intensity at multiple sampling locations along a set of gauge lines 208. Note that gauge lines 208 are concentrated around the risky area (i.e., the pinch) of polygon 204. On the other hand, the bottom plot in FIG. 2 illustrates a “center-line” based pinching check, wherein the intensity evaluations are performed along a single gauge at the lowest point (assuming dark field mask is used) of the intensity profile along a center line 210 (i.e., the long dashed line). Note that, contrary to the contour-based LRC approach, the check-figure based LRC typically does not compute the full contours of a layout, and hence, is computationally efficient.
When performing an LRC verification on a double-patterning process, the two masks associated with the two patterning steps have to be verified together to ensure that the printed pattern from each of the masks does not have pinching problems, and also that the combined patterns from both masks do not have bridging problems. Between the two LRC approaches described above, the contour-based verification is presently the preferred choice. This is because the two patterning steps involve two separate masks which are corrected using different lithography models, and because the two patterning steps do not share a common intensity field due to the etch step that occurs in between. For example, in one technique (see George E. Bailey et al., “Double pattern EDA solutions for 32 nm HP and beyond,” Proceedings of SPIE, volume 6521, Design for Manufacturability through Design-Process Integration, March 2007), contours of the two masks' patterns are first simulated with their respective models. Next, the contours for the two masks are OR'ed together, and LRC is conducted on the combined contour. Unfortunately, this contour-based LRC technique can be extremely time-consuming because contour simulation requires dense intensity evaluation over the entire mask layout.
Hence, there is a need for efficient techniques and systems for performing lithography verification for a DPT process.